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--- mse-em-board:memory [2020/04/17 15:30] – external edit 127.0.0.1
+++ mse-em-board:memory [2020/09/29 15:45] (current) – adm-hga3
@@ Line 3: / Line 3: @@
 The MSE-Embedded platform contains two SDRAM and one parallel flash memory as indicated in the below figure.
-{{ :huce:microlab:projects:internal:mse-em-board:mse-em-board_memory.jpg?direct&400 |}}
+{{ :mse-em-board:mse-em-board_memory.jpg?direct&400 |}}
 ===== SDRAM information =====
-The MSE-Embedded board contains two 16MByte mobile low-power SDR SDRAM. The datasheets can be found {{:huce:microlab:projects:internal:128mb_sdram.pdf| here}}.
+The MSE-Embedded board contains two 16MByte mobile low-power SDR SDRAM. The datasheets can be found {{:mse-em-board:128mb_sdram.pdf| here}}.
-These SDRAM can be used with the external SDRAM memory controller of QSYS. The below tables indicate the FPGA-pins to which the SDRAM is connected. And {{:huce:microlab:projects:internal:mse-em-board:sdram.tcl|here}} you find an example tcl script that can be used for pin-assignment in Quartus.
+These SDRAM can be used with the external SDRAM memory controller of QSYS. The below tables indicate the FPGA-pins to which the SDRAM is connected. And {{:mse-em-board:sdram.tcl|here}} you find an example tcl script that can be used for pin-assignment in Quartus.
 **SDRAM U3**
@@ Line 246: / Line 246: @@
 ===== Flash information =====
-The MSE-Embedded board contains besides the FPGA-configuration FLASH also a 32MByte parallel FLASH memory. The datasheets of this component is available {{:huce:microlab:projects:internal:mse-em-board:parallel_flash_p30-65nm_256mb.pdf|here}}.
+The MSE-Embedded board contains besides the FPGA-configuration FLASH also a 32MByte parallel FLASH memory. The datasheets of this component is available {{:mse-em-board:parallel_flash_p30-65nm_256mb.pdf|here}}.
-{{:huce:microlab:projects:internal:mse-em-board:flash_loader_an478.pdf|This application note}} explains the use of the FPGA-based parallel flash loader (PFL) in programming a parallel flash device before configuring an FPGA through the active parallel (AP) configuration scheme.
+{{:mse-em-board:flash_loader_an478.pdf|This application note}} explains the use of the FPGA-based parallel flash loader (PFL) in programming a parallel flash device before configuring an FPGA through the active parallel (AP) configuration scheme.
-The below tables indicate the FPGA-pins to which the FLASH is connected. And {{:huce:microlab:projects:internal:mse-em-board:flash.tcl|here}} you find an example tcl script that can be used for pin-assignment in Quartus.
+The below tables indicate the FPGA-pins to which the FLASH is connected. And {{:mse-em-board:flash.tcl|here}} you find an example tcl script that can be used for pin-assignment in Quartus.