Memory components
The MSE-Embedded platform contains two SDRAM and one parallel flash memory as indicated in the below figure.
SDRAM information
The MSE-Embedded board contains two 16MByte mobile low-power SDR SDRAM. The datasheets can be found here.
These SDRAM can be used with the external SDRAM memory controller of QSYS. The below tables indicate the FPGA-pins to which the SDRAM is connected. And here you find an example tcl script that can be used for pin-assignment in Quartus.
SDRAM U3
<html> <b>Address bus:</b> <table align=“center” style=“float:center” border=1> <tr> <th>Address bit:</th> <td>12</td> <td>11</td> <td>10</td> <td>9</td> <td>8</td> <td>7</td> <td>6</td> <td>5</td> <td>4</td> <td>3</td> <td>2</td> <td>1</td> <td>0</td> </tr> <tr> <th>FPGA-pin:</th> <td>PIN_AB4</td> <td>PIN_AA5</td> <td>PIN_U7</td> <td>PIN_Y7</td> <td>PIN_Y10</td> <td>PIN_AA4</td> <td>PIN_W8</td> <td>PIN_W10</td> <td>PIN_Y8</td> <td>PIN_Y6</td> <td>PIN_W6</td> <td>PIN_Y3</td> <td>PIN_Y4</td> </tr> </table> <b>Data bus:</b> <table align=“center” style=“float:center” border=1> <tr> <th>Data bit:</th> <td>15</td> <td>14</td> <td>13</td> <td>12</td> <td>11</td> <td>10</td> <td>9</td> <td>8</td> <td>7</td> <td>6</td> <td>5</td> <td>4</td> <td>3</td> <td>2</td> <td>1</td> <td>0</td> </tr> <tr> <th>FPGA-pin:</th> <td>PIN_AB10</td> <td>PIN_AB9</td> <td>PIN_AA10</td> <td>PIN_AB8</td> <td>PIN_AA9</td> <td>PIN_AB7</td> <td>PIN_AA8</td> <td>PIN_AA7</td> <td>PIN_T11</td> <td>PIN_U9</td> <td>PIN_T10</td> <td>PIN_V8</td> <td>PIN_T9</td> <td>PIN_U8</td> <td>PIN_T8</td> <td>PIN_V7</td> </tr> </table> <b>Control signals:</b> <table align=“center” style=“float:center” border=1> <tr> <th>Function:</th><th>short:</th><th>FPGA-pin:</th> </tr> <tr> <td>Bank Select high</td><td>BA[1]</td><td>PIN_U11</td> </tr> <tr> <td>Bank Select low</td><td>BA[0]</td><td>PIN_V11</td> </tr> <tr> <td>Byte Select high</td><td>DQM[1]</td><td>PIN_AB5</td> </tr> <tr> <td>Byte Select low</td><td>DQM[0]</td><td>PIN_V9</td> </tr> <tr> <td>Clock enable</td><td>CKE</td><td>PIN_W7</td> </tr> <tr> <td>Clock</td><td>CLK</td><td>PIN_AA3</td> </tr> <tr> <td>Colum address select (active low)</td><td>nCAS</td><td>PIN_V10</td> </tr> <tr> <td>Row address select (active low)</td><td>nRAS</td><td>PIN_U10</td> </tr> <tr> <td>Chip select (active low)</td><td>nCS</td><td>PIN_V6</td> </tr> <tr> <td>Write enable (active low)</td><td>nWE</td><td>PIN_V5</td> </tr> </table> </html>
SDRAM U4
<html> <b>Address bus:</b> <table align=“center” style=“float:center” border=1> <tr> <th>Address bit:</th> <td>12</td> <td>11</td> <td>10</td> <td>9</td> <td>8</td> <td>7</td> <td>6</td> <td>5</td> <td>4</td> <td>3</td> <td>2</td> <td>1</td> <td>0</td> </tr> <tr> <th>FPGA-pin:</th> <td>PIN_AB15</td> <td>PIN_AA16</td> <td>PIN_V12</td> <td>PIN_Y17</td> <td>PIN_AB14</td> <td>PIN_AA15</td> <td>PIN_AA13</td> <td>PIN_AA14</td> <td>PIN_AB13</td> <td>PIN_W15</td> <td>PIN_W14</td> <td>PIN_W13</td> <td>PIN_Y13</td> </tr> </table> <b>Data bus:</b> <table align=“center” style=“float:center” border=1> <tr> <th>Data bit:</th> <td>15</td> <td>14</td> <td>13</td> <td>12</td> <td>11</td> <td>10</td> <td>9</td> <td>8</td> <td>7</td> <td>6</td> <td>5</td> <td>4</td> <td>3</td> <td>2</td> <td>1</td> <td>0</td> </tr> <tr> <th>FPGA-pin:</th> <td>PIN_AB20</td> <td>PIN_AB19</td> <td>PIN_AA20</td> <td>PIN_AB18</td> <td>PIN_AA19</td> <td>PIN_AB17</td> <td>PIN_AA18</td> <td>PIN_AA17</td> <td>PIN_R15</td> <td>PIN_V14</td> <td>PIN_T14</td> <td>PIN_U14</td> <td>PIN_R14</td> <td>PIN_V13</td> <td>PIN_T13</td> <td>PIN_U13</td> </tr> </table> <b>Control signals:</b> <table align=“center” style=“float:center” border=1> <tr> <th>Function:</th><th>short:</th><th>FPGA-pin:</th> </tr> <tr> <td>Bank Select high</td><td>BA[1]</td><td>PIN_V16</td> </tr> <tr> <td>Bank Select low</td><td>BA[0]</td><td>PIN_U17</td> </tr> <tr> <td>Byte Select high</td><td>DQM[1]</td><td>PIN_AB16</td> </tr> <tr> <td>Byte Select low</td><td>DQM[0]</td><td>PIN_U15</td> </tr> <tr> <td>Clock enable</td><td>CKE</td><td>PIN_W17</td> </tr> <tr> <td>Clock</td><td>CLK</td><td>PIN_T16</td> </tr> <tr> <td>Colum address select (active low)</td><td>nCAS</td><td>PIN_U16</td> </tr> <tr> <td>Row address select (active low)</td><td>nRAS</td><td>PIN_V15</td> </tr> <tr> <td>Chip select (active low)</td><td>nCS</td><td>PIN_U12</td> </tr> <tr> <td>Write enable (active low)</td><td>nWE</td><td>PIN_T15</td> </tr> </table> </html>
Flash information
The MSE-Embedded board contains besides the FPGA-configuration FLASH also a 32MByte parallel FLASH memory. The datasheets of this component is available here.
This application note explains the use of the FPGA-based parallel flash loader (PFL) in programming a parallel flash device before configuring an FPGA through the active parallel (AP) configuration scheme.
The below tables indicate the FPGA-pins to which the FLASH is connected. And here you find an example tcl script that can be used for pin-assignment in Quartus.
Flash
<html> <b>Address bus:</b> <table align=“center” style=“float:center” border=1> <tr> <th>Address bit:</th> <td>23</td> <td>22</td> <td>21</td> <td>20</td> <td>19</td> <td>18</td> <td>17</td> <td>16</td> </tr> <tr> <th>FPGA-pin:</th> <td>PIN_G18</td> <td>PIN_B22</td> <td>PIN_B21</td> <td>PIN_C20</td> <td>PIN_A6</td> <td>PIN_A7</td> <td>PIN_B9</td> <td>PIN_A9</td> </tr> <tr> <th>Address bit:</th> <td>15</td> <td>14</td> <td>13</td> <td>12</td> <td>11</td> <td>10</td> <td>9</td> <td>8</td> </tr> <tr> <th>FPGA-pin:</th> <td>PIN_B10</td> <td>PIN_F11</td> <td>PIN_E11</td> <td>PIN_B13</td> <td>PIN_A13</td> <td>PIN_B14</td> <td>PIN_A14</td> <td>PIN_D13</td> </tr> <tr> <th>Address bit:</th> <td>7</td> <td>6</td> <td>5</td> <td>4</td> <td>3</td> <td>2</td> <td>1</td> <td>0</td> </tr> <th>FPGA-pin:</th> <td>PIN_C13</td> <td>PIN_B15</td> <td>PIN_A15</td> <td>PIN_F13</td> <td>PIN_E14</td> <td>PIN_B17</td> <td>PIN_A17</td> <td>PIN_B18</td> </tr> </table> <b>Data bus:</b> <table align=“center” style=“float:center” border=1> <tr> <th>Data bit:</th> <td>15</td> <td>14</td> <td>13</td> <td>12</td> <td>11</td> <td>10</td> <td>9</td> <td>8</td> <td>7</td> <td>6</td> <td>5</td> <td>4</td> <td>3</td> <td>2</td> <td>1</td> <td>0</td> </tr> <tr> <th>FPGA-pin:</th> <td>PIN_B6</td> <td>PIN_C8</td> <td>PIN_C7</td> <td>PIN_C4</td> <td>PIN_B3</td> <td>PIN_A3</td> <td>PIN_F8</td> <td>PIN_B4</td> <td>PIN_C6</td> <td>PIN_F10</td> <td>PIN_A5</td> <td>PIN_B7</td> <td>PIN_B8</td> <td>PIN_A8</td> <td>PIN_D1</td> <td>PIN_K1</td> </tr> </table> <b>Control signals:</b> <table align=“center” style=“float:center” border=1> <tr> <th>Function:</th><th>short:</th><th>FPGA-pin:</th> </tr> <tr> <td>Address valid</td><td>nADV</td><td>PIN_F20</td> </tr> <tr> <td>Chip enable</td><td>nCE</td><td>PIN_E2</td> </tr> <tr> <td>Clock</td><td>DCLK</td><td>PIN_K2</td> </tr> <tr> <td>Output enable</td><td>nOE</td><td>PIN_E21</td> </tr> <tr> <td>Reset</td><td>nRESET</td><td>PIN_E4</td> </tr> <tr> <td>Write enable</td><td>nWE</td><td>PIN_E22</td> </tr> <tr> <td>Param Die</td><td>ParamDie</td><td>PIN_E9</td> </tr> <tr> <td>Wait: indicates data valid</td><td>WAIT</td><td>PIN_E7</td> </tr> </table> </html>