mse-em-board:memory

Memory components

The MSE-Embedded platform contains two SDRAM and one parallel flash memory as indicated in the below figure.

The MSE-Embedded board contains two 16MByte mobile low-power SDR SDRAM. The datasheets can be found here.

These SDRAM can be used with the external SDRAM memory controller of QSYS. The below tables indicate the FPGA-pins to which the SDRAM is connected. And here you find an example tcl script that can be used for pin-assignment in Quartus.

SDRAM U3

Address bus:

Address bit: 12 11 10 9 8 7 6 5 4 3 2 1 0
FPGA-pin: PIN_AB4 PIN_AA5 PIN_U7 PIN_Y7 PIN_Y10 PIN_AA4 PIN_W8 PIN_W10 PIN_Y8 PIN_Y6 PIN_W6 PIN_Y3 PIN_Y4
Data bus:
Data bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FPGA-pin: PIN_AB10 PIN_AB9 PIN_AA10 PIN_AB8 PIN_AA9 PIN_AB7 PIN_AA8 PIN_AA7 PIN_T11 PIN_U9 PIN_T10 PIN_V8 PIN_T9 PIN_U8 PIN_T8 PIN_V7
Control signals:
Function:short:FPGA-pin:
Bank Select highBA[1]PIN_U11
Bank Select lowBA[0]PIN_V11
Byte Select highDQM[1]PIN_AB5
Byte Select lowDQM[0]PIN_V9
Clock enableCKEPIN_W7
ClockCLKPIN_AA3
Colum address select (active low)nCASPIN_V10
Row address select (active low)nRASPIN_U10
Chip select (active low)nCSPIN_V6
Write enable (active low)nWEPIN_V5

SDRAM U4

Address bus:

Address bit: 12 11 10 9 8 7 6 5 4 3 2 1 0
FPGA-pin: PIN_AB15 PIN_AA16 PIN_V12 PIN_Y17 PIN_AB14 PIN_AA15 PIN_AA13 PIN_AA14 PIN_AB13 PIN_W15 PIN_W14 PIN_W13 PIN_Y13
Data bus:
Data bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FPGA-pin: PIN_AB20 PIN_AB19 PIN_AA20 PIN_AB18 PIN_AA19 PIN_AB17 PIN_AA18 PIN_AA17 PIN_R15 PIN_V14 PIN_T14 PIN_U14 PIN_R14 PIN_V13 PIN_T13 PIN_U13
Control signals:
Function:short:FPGA-pin:
Bank Select highBA[1]PIN_V16
Bank Select lowBA[0]PIN_U17
Byte Select highDQM[1]PIN_AB16
Byte Select lowDQM[0]PIN_U15
Clock enableCKEPIN_W17
ClockCLKPIN_T16
Colum address select (active low)nCASPIN_U16
Row address select (active low)nRASPIN_V15
Chip select (active low)nCSPIN_U12
Write enable (active low)nWEPIN_T15

The MSE-Embedded board contains besides the FPGA-configuration FLASH also a 32MByte parallel FLASH memory. The datasheets of this component is available here.

This application note explains the use of the FPGA-based parallel flash loader (PFL) in programming a parallel flash device before configuring an FPGA through the active parallel (AP) configuration scheme.

The below tables indicate the FPGA-pins to which the FLASH is connected. And here you find an example tcl script that can be used for pin-assignment in Quartus.

Flash

Address bus:

Address bit: 23 22 21 20 19 18 17 16
FPGA-pin: PIN_G18 PIN_B22 PIN_B21 PIN_C20 PIN_A6 PIN_A7 PIN_B9 PIN_A9
Address bit: 15 14 13 12 11 10 9 8
FPGA-pin: PIN_B10 PIN_F11 PIN_E11 PIN_B13 PIN_A13 PIN_B14 PIN_A14 PIN_D13
Address bit: 7 6 5 4 3 2 1 0
FPGA-pin: PIN_C13 PIN_B15 PIN_A15 PIN_F13 PIN_E14 PIN_B17 PIN_A17 PIN_B18
Data bus:
Data bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FPGA-pin: PIN_B6 PIN_C8 PIN_C7 PIN_C4 PIN_B3 PIN_A3 PIN_F8 PIN_B4 PIN_C6 PIN_F10 PIN_A5 PIN_B7 PIN_B8 PIN_A8 PIN_D1 PIN_K1
Control signals:
Function:short:FPGA-pin:
Address validnADVPIN_F20
Chip enablenCEPIN_E2
ClockDCLKPIN_K2
Output enablenOEPIN_E21
ResetnRESETPIN_E4
Write enablenWEPIN_E22
Param DieParamDiePIN_E9
Wait: indicates data validWAITPIN_E7

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  • Last modified: 2020/09/29 17:45
  • by adm-hga3